This invention relates generally to discrete cosine transform (DCT) based compression and decompression of data, and more particularly the invention relates to enhanced speed of coding and decoding operations in implementing such algorithms.
Image compression is used in reducing large volumes of data in digitized images for convenient and economical storage and for transmission across communication networks having limited bandwidth. Image compression technology is important in digital still video cameras, color scanners, color printers, color fax machines, computers, and multimedia.
The joint photographic experts group (JPEG) has established a color image data compression standard and a draft after compression standard for use in a variety of still image applications. Compression employs DCT-based processes operating on discrete blocks of the image. The DCT coefficients are then quantized, for example based on measurements of the threshold for visibility. For coding, an 8.times.8 pixel array of DCT coefficient is reorganized into a one dimensional list using a zigzag sequence which tends to concentrate coefficients expressing the lowest spatial frequencies at lower indices with the DC component being number 0 in the zigzag. The quantized AC coefficients are then encoded using a Huffman coder. Finally, headers and markers are inserted in the compressed file along with bit and byte stuffings for JPEG data compatibility. FIG. 1 illustrates the JPEG baseline compression algorithm.
The compressed data can then be stored (as in an electronic still camera) or transmitted efficiently over a limited bandwidth communication network. Reconstruction of the image requires a reverse process in which the headers and markers are extracted, the Huffman code is decoded, coefficients are dequantized, and an inverse DCT (IDCT) operation is performed on the coefficients.
Zoran Corporation (assignee herein) has developed a chip set for image compression including a discrete cosine transform (DCT) processor designated ZR36020 and an image compression coder/decoder designated ZR36040, as shown in FIG. 2. The chip set employs an algorithm for high quality compression of continuous tone color or monochrome images. The DCT processor implements both forward and inverse discrete cosine transform computations on 8.times.8 pixel blocks, while the coder/decoder implements the quantization, dequantization, Huffman encoding and decoding of the image compression algorithm. The chip set reduces the large data size required to store and transmit digital images by removing statistical redundancies in the image data while maintaining the ability to reconstruct a high quality image. For example, in digital still video cameras, the chip set enables the use of 1M byte solid state memory card instead of a 4M byte hard disk to store 22 768.times.480 pixel images. The chip set also reduces the time required to transmit a 768.times.480 pixel image over a standard 9600 bits per second telephone line from 15 minutes to 40 seconds. The chip set has been optimized for use in digital still video cameras, color video printers, fixed bit rate image transmission devices, security systems, and cost sensitive image compression systems.
The quantization of the coefficients is done by using quantization tables. The compression ratio is controlled by scaling the quantization tables with a uniform scale factor. A large scale factor results in a high compression ratio and vice versa. The mechanism to determine the scale factor is by using the two passes: the first pass through the image is done with an initial scale factor (ISF). The quantization tables are scaled with the initial scale factor. Code volume needed for encoding the quantized DCT coefficients is accumulated during this pass using the Huffman tables (ACV data). This code volume is then used as the activity measure of the image.
Image compression frequently involves processing of large amounts of data in high data rates. The requirements from the processing system both when encoding the data and decoding the data are enormous and grow linearly with the number of pixels in the image. The requirements are even heavier in encoding when more than one pass through the data is required for gathering statistics. The encoding time grows linearly with the number of passes through the image.
One way to enhance the processing speed is to build more complex devices which have more hardware and process data faster. However, more complex devices are expensive, impractical for lower speed applications, and possibly impossible to implement at this time.
The present invention is directed to providing a device which can operate independently for standard rate systems and which includes minimum functions which support operation of a plurality of devices in parallel.